 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NJU26209 DAEP Decoder General Description The NJU26209 is a digital signal processor that provides the function of DAEP (Dolby Automotive Entertainment Program). A location of sound image forward is possible without a center speaker by all seats in the car. The applications of NJU26209 are suitable for Car Audio, Car Navigation system and other audio products. Package Features -Software DAEP (Dolby Automotive Entertainment Program) Pro Logic II Automotive (Advanced Surround Fader, Center Image Control) Bass Management Time Alignment Master Volume Input Trim Channel Trim -Hardware 24bit Fixed-point Digital Signal Processing Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit Digital Audio Interface : 4 Input ports / 4 Output ports Digital Audio Format : I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs Master / Slave Mode Microcomputer Interface I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps) 4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data) Operating Voltage : VDD = VDDPLL = 1.8V : VDDIO = 3.3V Input Terminal : +5.0V Input tolerant Package : SSOP44 (Pb-Free) NJU26209V * The detail hardware specification of the NJU26209 is described in the " NJU26200 Series Hardware Data Sheet". Ver.2008-12-04 -1- NJU26209 Hardware Block Diagram AD1/SDIN AD2/SSb DSP ARITHMETIC UNIT SCL/SCK SERIAL HOST INTERFACE PROGRAM CONTROL SERIAL AUDIO INTERFACE BCKO BCKO LRO L/Rout SDA/SDOUT 242424-BIT 24-BIT MULTIPLIER RESETb MCK CLK CLKOUT ALU SDO SDO1 SDO2 SDO2 SDO3 SDO3 SDO0 SDO0 SDI0~3 SDI0~3 BCKI LRI C/SWout C/SWout LM/RMout LB/RBout /RB TIMING GENERATOR / PLL Input Input ADDRESS ADDRESS GENERATION UNIT PROC DATA RAM FIRMWARE ROM General I/O INTERFACE MUTEb SEL WDC Fig. 1 NJU26209 Hardware Block Diagram -2- Ver.2008-12-04 NJU26209 Function Block Diagram DAEP L SDI0 R L/R SDI1 Advanced Fader / Mixer LM SDI2 C/SW Input Trimmer LS SDI3 LS/RS RS Pro Logic II 5ch LS RS RM LS RS LM RM LS RS Bass Management Time Alignment LM RM Master Volume & Channel Trim LS RS C Pro Logic II 3ch L CPLII R C R C L Phantom Center R C Time Alignment L Time Alignment R C R C SW LM RM LS RS SDO0 SDO3 SDO2 L L SDO1 Time Alignment LFE Time Alignment SW Fig. 2 Function Block Diagram (Firmware) Ver.2008-12-04 -3- NJU26209 Pin Configuration SDI3 SDI2 SDI1 SDI0 LRI VDDIO BCKI VSS VDD TEST MUTEb WDC PROC VSSIO VDDIO SEL VDDPLL VSSPLL VSS VDD CLKOUT CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NJU26209 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VDD VSS VSSIO VDDIO SDO0 SDO1 SDO2 SDO3 LRO BCKO MCK VDDIO SDA/SDOUT SCL/SCK AD2/SSb AD1/SDIN TEST TEST TEST RESETb VDDIO VSSIO SSOP44 Fig. 3 NJU26209 Pin Configuration -4- Ver.2008-12-04 NJU26209 Pin Description Table 1 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol SDI3 SDI2 SDI1 SDI0 LRI VDDIO BCKI VSS VDD TEST * MUTEb * WDC * PROC * VSSIO VDDIO SEL VDDPLL VSSPLL VSS VDD CLKOUT CLK VSSIO VDDIO RESETb TEST TEST TEST AD1/SDIN AD2/SSb SCL/SCK SDA/SDOUT VDDIO MCK BCKO LRO SDO3 SDO2 SDO1 SDO0 VDDIO VSSIO VSS VDD I/O I I I I I I I I OD I I O I I I I I I I I I/O O O O O O O O Function Audio Data Input ch.3 (LS/RS) Audio Data Input ch.2 (C/SW) Audio Data Input ch.1 (L/R) Audio Data Input ch.0 (L/R) LR Clock Input I/O Power Supply +3.3V Bit Clock Input DSP Core Power Supply GND DSP Core Power Supply +1.8V for test connect with VSSIO through 3.3-ohm resistance. Master Volume Status after reset `1': 0dB, `0': Mute Watchdog Clock output pin (Open drain output) Signal Processing after reset `1': Normal Processing, `0': Waiting for a Command without Processing I/O Power Supply GND I/O Power Supply +3.3V 2 Host Interface Selection `1': Serial Interface, `0': I C bus PLL Power Supply +1.8V PLL Power Supply GND DSP Core Power Supply GND DSP Core Power Supply +1.8V OSC Clock Output OSC Clock Input (12.288MHz) I/O Power Supply GND I/O Power Supply +3.3V Reset (RESETb='0': DSP Reset) for test (connect to VDDIO) for test (connect to VSSIO) for test (connect to VSSIO) 2 2 I C Address (I C mode) / Serial In (4-wire serial mode) 2 2 I C Address (I C mode) / Serial enable (4-wire serial mode) 2 2 I C SCL (I C mode) / Serial clock (4-wire serial mode) 2 2 I C SDA (I C mode) / Serial Out (4-wire serial mode) I/O Power Supply +3.3V A/D, D/A clock output (buffer output of a CLK pin) Bit Clock Output LR Clock Output Audio Data Output ch.3 (LM/RM) Audio Data Output ch.2 (C/SW) Audio Data Output ch.1 (L/R) Audio Data Output ch.0 (LS/RS) I/O Power Supply +3.3V I/O Power Supply GND DSP Core Power Supply GND DSP Core Power Supply +1.8V Note : I : Input O : Output OD : Open Drain Output I/O : Bi-directional Pins symbol with * : Connect with VDDIO or VSSIO through 3.3k resistance Ver.2008-12-04 -5- NJU26209 The NJU26209 audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first Right-justified. The NJU26209 audio interface provides four data inputs, SDI0, SDI1, SDI2 and SDI3, and four data outputs, SDO0, SDO1, SDO2 and SDO3 as shown in table 2 and 3. The input serial data is selected by the firmware command. Table 2 Pin No. 4 3 2 1 Serial Audio Input Pin Symbol SDI0 SDI1 SDI2 SDI3 Description Stereo input Multi channel input Audio Data Input (L/R) Audio Data Input (L/R) (SDI0/SDI1 pin select) (SDI0/SDI1 pin select) None Audio Data Input 2 (C/SW) None Audio Data Input 3 (LS/RS) Audio Interface Table 3 Serial Audio Output Pin Pin No. Symbol Description 40 SDO0 Audio Data Output 0 (LS/RS) 39 SDO1 Audio Data Output 1 (L/R) 38 SDO2 Audio Data Output 2 (C/SW) 37 SDO3 Audio Data Output 3 (LM/RM) The NJU26209 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or 4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The detail I2C bus and 4-Wire Serial bus information are described in the `NJU26200 Series Hardware Data Sheet'. Table 4 Serial Host Interface Pin Descriptions Pin No. Symbol Setting Low 16 SEL High Table 5 Pin No. 29 30 31 32 Host Interface Host Interface I2C Bus Interface 4-Wire Serial Interface Serial Host Interface Pin Description Symbol 2 (I C /Serial) AD1/SDIN AD2/SSb SCL/SCK SDA/SDOUT 2 2 I C bus Interface 4-Wire Serial Interface Serial data input Slave select Serial Clock Serial data output (CMOS Output) 2 I C Address Select Bit1 2 I C Address Select Bit2 Serial Clock Serial Data Input/Output (Open Drain output) 2 Note: When I C Bus is selected, this pin is a bi-directional Open Drain output. This pin, which is assigned for I C Bus, requires a pull-up resistance. When 4-Wire Serial bus is selected, the SDA/SDOUT pin is CMOS output. The SDA/SDOUT pin isn't 5.0V Input tolerant. -6- Ver.2008-12-04 NJU26209 I2C Bus When the NJU26209 is configured for I2C bus communication in SEL="Low", the serial host interface transfers data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) Table 6 I C Bus Interface Slave address 2 bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 AD2 bit2 0 0 1 1 AD1 bit1 0 1 0 1 R/W bit0 R/W Start bit Slave Address ( 7bit ) R/W bit ACK * SLAVE address is 0 when AD1/2 is "Low". SLAVE address is 1 when AD1/2 is "High". * SLAVE address is 0 when R/W is "W". SLAVE address is 1 when R/W is "R". Note: Both "Standard-Mode (100kbps)" and "Fast-Mode (400kbps)" data transfer rate are supported. 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1="High" during the Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting SSb = "Low". Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is latched on the falling transitions of SSb. SDOUT is always CMOS output. SDOUT does not require a pull-up resistance. SSb SCK SDIN SDOUT unstable bit7 MSB bit6 bit6 bit5 bit5 bit1 bit1 bit0 LSB bit7 bit0 unstable Fig. 4 4-Wire Serial Interface Timing Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb="High". When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes "High". Ver.2008-12-04 -7- NJU26209 Pin setting The NJU26209 operates default command setting after resetting the NJU26209. In addition, the NJU26209 restricts operation at power on by setting PROC pin and MUTEb pin. These pins are input pin. However, these pins operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3k resistance. Table 7 Pin No. 13 11 Pin setting Symbol Setting "High" PROC "Low" MUTEb "High" "Low" Function The NJU26209 operates default setting after reset. The NJU26209 does not operate after reset. Sending start command is required for starting operation. Master volume is set 0dB after reset. Master volume is set mute after reset. WatchDog Clock The NJU26209 outputs clock pulse through WDC (Pin No.12) during normal operation. The WDC clock is useful to check the status of the NJU26209 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26209. When the WDC clock pulse is lost or not normal clock cycle, the NJU26209 does not operate correctly. Then reset the NJU26209 and set up the NJU26209 again. The WDC clock is able to be variable for 0msec to 100msec by command. Default setting of WDC clock is 100msec. The WDC pin is open drain output. The WDC pin setting (Table 8) Table 8 WDC pin setting Pin No. 12 Symbol WDC pin is used. WDC WDC pin is not used. Setting Connect with VDDIO through 3.3k resistance. Connect with VSSIO through 3.3k resistance. Do not open WDC pin. Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing. In slave mode, when there is no input of BCKI/LRI, WDC can't output. It is required to set up a sampling rate correctly. -8- Ver.2008-12-04 NJU26209 Firmware Command Table Host processor can control the NJU26209 via I2C bus or 4-Wire serial bus interface. The following table summarizes the available user commands. Table 9 Command Table No. Command Description 1 Set Task Command 2 System State Command 3 Sample rate Select Command 4 Smooth Control Config Command 5 Master Volume Control Command 6 Channel Trim Control Command 7 Input Trim Control Command 8 DAEP Balance Control Command 9 DAEP Phantom Center Config Command 10 Pro Logic II Shelf Filter Config Command 11 Bass Management Config Command 12 Bass Management LFE Trim Command 13 Bass Management Center Trim Command 14 Bass Management L/R Trim Command 15 Bass Management LS/RS Trim Command 16 Front Delay Control Command 17 Middle Delay Control Command 18 Surround Delay Control Command 19 Center Delay Control Command 20 Subwoofer Delay Control Command 21 PNG Mode Command 22 Firmware Version Number Request Command 23 DSP Reset Command 24 Start Command 25 Nop Command Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (Dolby) is required. Response of status NJU26209 returns the response of 4 types to the host controller. Table 10 Response of status Response Status : Command Accepted Status : Command Error Status : Command Process Status : Not Ready Command 0x80 0x81 0x82 0x83 Remark Reception OK Reception ERROR Command processing Initialization Ver.2008-12-04 -9- NJU26209 License Information The Word "DOLBY", "Pro Logic II", DAEP and the double D mark are trademarks of Dolby Laboratories. The NJU26209 can only be delivered to licensees of Dolby Laboratories. Please refer to the licensing application manual issued by Dolby Laboratories. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 - Ver.2008-12-04 |
Price & Availability of NJU26209
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |